• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
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    • 专利摘要:
    In the window comparison / mode, there is provided a timing comparison circuit for a device test apparatus that can eliminate an off time in which a fail cannot be detected. The first and second window strobe pulse generation circuits S / RFF1 and S / RFF2 alternately generating window strobe pulses, and the duration and level comparators of the window strobe pulses supplied from these window strobe pulse generation circuits, respectively. First and second fail detection circuits 5a and 5b and first and second electricave circuits 8 and 9 for detecting whether a fail signal is present in the output signal from Interleave the first strobe pulse into an odd-cycle strobe pulse train and an odd-cycle strobe pulse train, and operate the first window strobe pulse generation circuit by an odd-cycle first strobe pulse train. The second window strobe pulse generation circuit is operated by the first strobe pulse train of even periods and the second strobe pulse by the second interleave circuit. Are interleaved into the odd-numbered strobe pulse train and the even-numbered strobe pulse train, and the operation of the first window strobe pulse generation circuit is stopped by the second strobe pulse train of the odd-numbered cycle, and the second strobe pulse of the even-numbered cycle is stopped. The column stops the operation of the second window strobe pulse generation circuit, thereby generating odd period window strobe pulses and even period window strobe pulses from the first and second window strobe pulse generation circuits.
    公开号:KR19980046278A
    申请号:KR1019960064589
    申请日:1996-12-12
    公开日:1998-09-15
    发明作者:히로카츠 니이지마
    申请人:오오우라 히로시；가부시키가이샤 아드반테스트；
    IPC主号:
    专利说明:

    Timing Comparison Circuit for Device Tester
    1 is a block diagram showing a circuit configuration of a main part of a semiconductor memory test apparatus using the timing comparison circuit according to the present invention;
    2 is a timing diagram showing waveforms at various points of the circuit of FIG.
    3 is a timing diagram showing waveforms in other points of the circuit of FIG.
    4 is a block diagram showing a circuit portion including a timing comparison circuit of a conventional semiconductor memory test apparatus;
    5 is a timing diagram showing waveforms at various points of the circuit of FIG.
    FIG. 6 is a timing diagram similar to FIG. 5 showing the case where the off time is reduced in the circuit of FIG.
    [Background of invention]
    Technical Field of the Invention
    The present invention is a semiconductor memory test apparatus or other semiconductor device for testing defects in semiconductor memory such as random access memory (RAM), read only memory (ROM), and charge coupled device (CCD) memory. And a useful timing comparison circuit using a device testing apparatus including an apparatus for testing a defect of an electronic component or the like.
    Moreover, in order to facilitate understanding of the present invention, the following describes a case where the present invention is applied to a semiconductor memory test apparatus for testing a defect of a semiconductor memory, but the present invention tests various devices other than the semiconductor memory test apparatus. Naturally, it can be applied to the device.
    [Description of Related Technology]
    The semiconductor memory test apparatus, roughly speaking, consists of a timing generator, a test pattern generator, a waveform shaper, a logic comparator and a poor analysis memory. The test pattern generator responds to the reference clock, which is also supplied with timing, and analyzes and compares the address signals, test data signals, and control signals and logic signals supplied to the semiconductor memory to be tested (commonly referred to as a device under test (DUT)). Generates the expected data signal supplied to the memory. The address signal, the test data signal, and the control signal except the expected data signal are first input to the waveform shaper, where the waveforms are shaped into the waveforms required for the test of the memory under test and are applied to the memory under test.
    The memory under test is controlled to write or read test data by applying a control signal. That is, test data is sequentially written to the address of the memory under test specified by the address signal to which the control signal for writing is applied, and from the address of the memory under test specified by the address signal by the application of the control signal for reading. Recorded test data is read sequentially. The read data signal read out from the memory under test is given to a logic comparator, where it is compared with an expected data signal output from the test pattern generator. If the result of the comparison is inconsistent, the logical comparator outputs bad data, so-called FAIL data. Normally, logic "1" is output as fail data. On the other hand, if the comparison results match, the logical comparison unit outputs good data, that is, PASS data. Since the fail data is a logic "1", the pass data outputs a logic "1". The fail data is transferred and stored in the failure analysis memory, but the pass data is not stored.
    Before the data signal read out from the memory under test is logically compared with the expected data signal from the test pattern generator, the output signal level is first compared with the expected value level. A 1 "output (and hence a fail signal) is generated and within the allowable range. This fail signal or pass signal is then compared with the timing comparison clock generated from the timing generator. This timing comparison uses edge strobe pulses and the duration of the strobe pulses using edge comparison mode and window strobe pulses, which compare with the fail signal or the pass signal at only one point of the time when the strobe pulses are present. There are two window comparison modes for performing a fail signal or a pass signal and a fertilizer. This invention relates to the improvement of the timing comparison circuit of the window comparison mode which can remove glitches.
    First, an example of a conventional timing comparison unit in which the edge comparison mode and the window comparison mode can be converted and used is shown in the block diagram of FIG. 4 and the timing diagrams of FIGS. 5 and 6 for explaining the operation in the window comparison mode. It demonstrates with reference.
    The timing comparison unit shown in FIG. 4 is a mode switch SW for converting the first and second timing comparators 1 and 2, the timing comparison mode into the edge comparison mode and the window comparison mode, and the window comparison mode. And a multiplexer (MUX1) for converting and outputting the output of the timing comparator 5 and the timing comparator 2 including the window strobe pulse generation circuit operating at When the movable contact c of the mode switch SW is converted to the fixed contact a side to which the logic "0" output is supplied, the fixed contact b to which the logic "1" output is supplied is operated in the edge comparison mode. When it is converted to) side, it operates in window comparison mode. The example of illustration shows the state which operates in the window comparison mode because the movable contact c of the mode switch SW is converted to the stationary contact b side.
    In each cycle of a series of cycles constituting one test cycle, the output signal read from the device under test, in this example memory 1 under test (hereinafter referred to as DUT), is first transmitted to the level comparator 2 Where signal level is compared with expected level. The expected level has two comparison voltages (VOL) used when the output from the DUT 1 is a logic "1." In either case, when the path is a pass from the level comparator 2, the logic "0" fails. At that time, a logic " 1 " is output and transmitted to the first and second timing comparators CMP 1 and 2 of the timing comparator and the AND gate AND1 of the timing comparison circuit 5. As shown in FIG.
    The first timing comparator CMP1 is supplied from the timing generator 6 with a first strobe pulse STRB1 (see also 5B) having a pulse width of ¼ period T which is a clock for timing comparison in this example. The signal is compared with the fail signal (logical "1" output) or the pass signal (logical "0" output) output from the level comparator 2. As is apparent from FIG. 5, the pulse width of the first strobe pulse STRB1 is larger than the pulse width of the logic [1] output (fail signal) of the level comparator 2 (see also FIG. 5A). The second timing comparator CMP2 is supplied from the timing generator 6 with a second strobe pulse STRB2 (see also 5C) having a delay of ½ cycle than the first strobe pulse STRB1 but having the same pulse width. This is compared with a fail signal or a pass signal or a pass signal output from the same level comparator 2. Each of these timing comparators CMP1 and CMP2 outputs a logic "0" when the comparison result is a pass and a logic "1" when the comparison result is a fail. Furthermore, the first strobe pulse STRB1 is also supplied to the clock terminal of the first flip-flop FF1 between the first delay circuits 3, and the second strobe pulse STRB2 is supplied to the second delay circuit. It is also supplied to the clock terminal of the second flip-flop FF2 between (4).
    When the edge comparison mode is selected, a logic "0" (L level) output is supplied to the set terminal S of the multiplexer MUX1 and the clear terminal CL of the first flip-flop FF1. As a result, the multiplexer MUX1 is set to connect its input A to its output Q, and the first flip-flop FF1 is not in operation. Therefore, as a result of the comparison of the first timing comparator CMP1, the strobe pulse STRB1 delayed between the first delay circuit 3 is supplied to the clock terminal of the first flip-flop FF1. The strobe pulse STRB2 stored in the flip-flop FF1, and similarly, the comparison result of the second timing comparator CMP2 is delayed between the second delay circuits 4 at the clock terminal of the second flip-flop FF2. In the example of illustration, STRB2 'is supplied, and is stored in the 2nd flip-flop FF2 between the multiplexer MUX1.
    The fail data Df1 and Df2 stored in the first and second flip-flops FF1 and FF2 are transmitted to the theoretical comparator 7 where they are compared with expected data signals supplied from the test pattern generator.
    On the other hand, when the window comparison mode is selected, a logic "1" (H level) output is supplied to the set terminal S of the melt multiplexer MUX1 and the clear terminal CL of the first flip-flop FF1. . In this case, the multiplexer MUX1 is set to connect the input B to the output Q. On the other hand, even if the first flip-flop FF1 is cleared and the comparison result of the first timing comparator CMP1 is supplied to the data terminal D, its Q output remains the logic " 0 ". Therefore, only the output of the timing comparison circuit 5 operating in the window comparison mode is in a state where the second flip-flop FF2 can be stored between the multiplexer MUX1.
    In this example, the timing comparison circuit 5 is composed of the set-set flip-flop S / R-FF1 and the third flip-flop FF3 constituting the above-described AND gate AND1, the window strobe pulse generation circuit. It is.
    The first strobe pulse STRB1 is supplied from the timing generator 6 to the set terminal S of the set reset flip-flop S / R FF1, and the second strobe is supplied to the reset R terminal. The pulse STRB2 is supplied, and its Q output is connected to the other input of the AND gate AND1 and the clock terminal of the third flip-flop FF3. Since the logic "1" output is always applied to the data terminal D of the third flip-flop FF3, the reset flip-flop S / R-FF1 is supplied by supplying the first strobe pulse STRB1. ) Is set and a logic "1" is output from the Q output thereof, the Q output of the third flip-flop FF3 becomes a logic "1". Therefore, a logic " 0 " of the XQ output, which is the inverted output, is supplied to the B input of the multiplexer MUX1.
    When logic "1" is output from the Q output of the set reset flip-flop S / R FF1, the AND gate AND1 is enabled, so that the logic "1" from the level comparator 2, that is, a fail signal. When (Fig. 5A) is output and supplied to the AND gate AND1, this fail signal passes through the AND gate AND1 and is given to the clear terminal CL of the third flip-flop FF3. Therefore, since the third flip-flop FF3 is cleared and its XQ output becomes logic "1", the logic "1" is supplied from the B input of the multiplexer MUX1. The XQ output of the third flip-flop FF3 is logic " 1 " until the set reset flip-flop S / R-FF1 is set by the leading end of the first strobe pulse STRB1 of the next period. Fail) (see also 5K).
    In this way, the AND gate AND1 is reset by the second strobe pulse STRB2 after the set reset flip-flop S / R FF1 is set by the first strobe pulse STRB1. When the signal is enabled until and a fail signal (logical " 1 " output) comes from the level comparator 2, the signal is sent. In other words, the set reset flip-flop S / R FF1 rises at the leading end of the first strobe pulse STRB1 and falls at the leading end of the second strobe pulse STRB2 as shown in FIG. 5I. A window strobe pulse generation circuit for generating the window strobe pulses W · STRB is constituted, and AND gate AND1 is opened between the duration of the strobe pulses (period of logic " 1 "), and from the level comparator 2 When a logic "1" output (fail signal) comes, it is passed (see also 5J). Therefore, when a failure occurs, the set-up flip-flop S / R-FF1 is set by the leading end of the first strobe pulse STRB1 of the next period from the XQ output of the third flip-flop FF3. Until this, the logic " 1 " output (FIG. 5K) is supplied to the data terminal of the second flip-flop FF2 through the multiplexer MUX1.
    Thus, in the window comparison mode, only the window comparison result from the inverted output XQ of the third flip-flop FF3 supplied to the B input of the multiplexer MUX1 is stored in the second flip-flop FF2. .
    As described above, in the window comparison mode, the logic switch " 1 " (H level) signal is supplied to the mode switch SW as shown in Fig. 5AO, so that the clear terminal of the first flip-flop FF1 ( The logic " 1 " output is applied to the set terminal S of the CL and the multiplexer MUX1, and the Q output of the first flip-flop FF1 has the logic " 1 " L level). As shown in Fig. 5, for example, if a fail signal "1" (Fig. 5A) is generated from the level comparator 2 when the first strobe pulse STRB1 ends, this fail signal is an AND gate. The signal is input to the clear terminal CL of the third flip-flop FF3 after passing through AND1. Therefore, the fail signal shown in FIG. 5J is output from the AND gate AND1, the third flip-flop FF3 is cleared at the leading end of the fail signal, and the fail shown in FIG. 5K from the 2XQ output. The signal is supplied to the B input of the multiplexer MUX1. Therefore, the same fail signal (see also F) as the B input is output from the Q output of the multiplexer MUX1, and is supplied to the data terminal D of the second flip-flop FF2.
    As described above, the second terminal strobe pulse STRB2 is applied to the clock terminal of the second flip-flop FF2 by the second delay circuit 4 for a predetermined time (in this example, the second strobe pulse STRB2). Since the delayed strobe pulse STRB2 '(see also 5H) is supplied, the fail signal of the data terminal D of the second flip-flop FF2 at the time when this pulse STRB2' is applied 5F) begins to be stored in the second flip-flop FF2. Since the Q output of the second flip-flop FF2 is logic "1" until the pulse STRB2 'of the next period reaches the clock terminal, the fail signal shown in FIG. 5M is supplied to the logic comparator 7. .
    Thus, in the window comparison mode, between the first strobe pulse STRB1 and the second strobe pulse STRB2, which are clocks for timing comparison generated from the timing generator 6, in other words, the set reset flip-flop. While the comparison is made during the pulse duration of the window strobe pulse (W · STRB; FIG. 5I) generated from (S / R.FF1), as shown in FIG. 5K, the detected fail signal is actually the second. The flip-flop FF2 is stored in the first cycle of the next period when the pulse STRB2 'delayed by the second delay circuit 4 is supplied to the claw terminal of the second flip-flop FF2. Until the set-set flip-flop S / R-FF1 is set by the strobe pulse STRB1 (thus, the tip of the next window strobe pulse W-STRB) is turned on by the third flip-flop FF3. Until entered). Therefore, the portion shown by the oblique lines in the waveform of FIG. 5K is the fail extension data (the time that can be used to store the fail signal of the third flip-flop FF3 in the second flip-flop FF2).
    The time I until the window strobe pulse W · STRB of the next period rises after the completion of the period of the window strobe pulse W · STRB is called an off time. The timing of the signal and the pass signal cannot be compared. Therefore, a failure that occurred in this period cannot be detected.
    In order to shorten this off time period, it is necessary to extend the range of window comparison. In order to extend the range of window comparison, as shown by the arrow in FIG. 6, when the second strobe pulse STRB2 is delayed to approach the first strobe pulse STRB1 of the next period, the fail extension is performed. The area of the data (the oblique region in FIG. 6K) is reduced, and the minimum setup hold time required for storing the fail data from the third flip-flop FF3 in the second flip-flop FF2 is not satisfied ( Shorter than the minimum set-up hold time) and fail data cannot be stored. For this reason, this minimum setup / hold time is a time that can never be eliminated.
    The minimum set up / hold time is called the minimum off time Min, and for this reason, it is not possible to set the second strobe pulse STRB2 and the first strobe pulse STRB1 of the next period within this minimum off time period. . That is, it is necessary to provide a time interval of at least the minimum off time Min between the second strobe pulse STRB2 and the first strobe pulse STRB1 of the next period. In order to be able to detect a failure occurring within this minimum off-time period, conventionally, the DUT is tested by dividing the circuit into two parts with a timing shift. Therefore, there was a drawback of requiring twice the test period and very poor efficiency.
    [Overview of invention]
    SUMMARY OF THE INVENTION An object of the present invention is to provide a timing comparison circuit for a device test apparatus which can eliminate the off time in which a fail cannot be detected in the window comparison mode, and compare all data output from the device under test in a single test. will be.
    According to the present invention, the output signal from the level comparator is applied to the first and second window strobe pulse generation circuits that alternately generate the window strobe pulses, and the window strobe pulses supplied from the window strobe pulse generation circuits, respectively. First and second fail detection circuits for detecting whether a fail signal is present, and first and second interleaving circuits, wherein the first interleave circuit sends a first strobe pulse to an odd period of first Is interleaved into two pulse strings of the strobe pulse of and the first strobe pulse string of the even period, and the first window strobe pulse generation circuit is operated by the first strobe pulse string of the odd period and the second window strobe pulse The generation circuit is operated by a first strobe pulse train of even periods; The interleaving circuit interleaves the second strobe pulse to two pulse strings of the second strobe pulse string of odd periods and the second strobe pulse string of even periods, and the first window by the second strobe pulse string of odd periods. The operation of the strobe pulse generation circuit is stopped, and the operation of the second window strobe pulse generation circuit is stopped by the second strobe pulse train of even periods.
    Generating odd period window strobe pulses and even period window strobe pulses from the first and second window strobe pulse generation circuits, and generating a level comparator during the duration of the odd period window strobe pulses and the even period window strobe pulses; A timing comparison circuit is provided that operates in a window comparison mode configured to detect whether a fail has occurred in the data (signal) issued from the data.
    According to the timing comparison circuit of the above configuration, even if the timing of generating the second strobe pulse is approached to the timing of generating the first strobe pulse of the next period, or even if the timing of generating the first strobe pulse of the next period is the same, The output of the first and second fail detection circuits can be cleared at the leading end of the window strobe pulse of the next period immediately, but not at the leading end of the Winnow strobe pulse of the next period, thereby increasing the width of the fail confirmation data area. can do. Therefore, a fail extended zeta region longer than the minimum set-up / hold time (minimum off time) required for storing the outputs of the first and second fail detection circuits as a storage means can be secured, and the odd and even periods It is possible to eliminate the minimum off time in which the timing comparison between the window strobe pulses cannot be performed. Therefore, even if a failure occurred at any point in time by one test, the test time can be very shortened, and the test apparatus can be used very efficiently.
    Detailed Description of the Preferred Embodiments
    Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 3. Furthermore. In FIG. 1, the part corresponding to FIG. 4 is attached | subjected with the same code | symbol, and the description is abbreviate | omitted unless it is necessary.
    FIG. 1 shows one embodiment of a timing comparison circuit operating in the window comparison mode according to the present invention, and shows a case where this timing comparison circuit is applied to a semiconductor memory test apparatus. Like the conventional timing comparison unit shown in FIG. 4, the timing comparison unit shown in FIG. 1 also converts the movable contact c of the mode switch SW to the fixed contact a side to which the logic "0" output is supplied. It is configured to operate in the window comparison mode when operating in the edge comparison mode at the time and switching to the fixed contact b side to which the logic " 1 " output is supplied. As mentioned above, since this invention relates to the timing comparison circuit which operates in a window comparison mode, the operation | movement of a window comparison mode is mainly described below.
    The output signal to be read from DUT1 is first sent to level comparator 2, where the signal level is compared with the expected level. There are two expected levels: the comparison voltage VOH used when the output from DUT1 is logic "1" and the comparison voltage VOL used when the output from DUT1 is logic "0". The logic "0" is outputted in the case of a pass, and the logic "1" is outputted in the case of a failure, and this invention operates in the window comparison mode of the timing comparator, like the first and second timing comparators CMP1 and 2 of the timing comparator. Is transmitted to the first and second AND gates AND1 and AND2 of the timing comparison circuit 5.
    The first timing comparator CMP1 is supplied with a first strobe pulse STRB1 (see also 2B) having a pulse width of ¼ period T from the timing generator 6 and outputted from the level comparator 2. (Logical "1" output) or path signal (logical "0" output). The second timing comparator CMP 2 is supplied from the timing and generator 6 with a second strobe pulse STRB2 (see also 2C) having a delay of ½ cycles from the first strobe pulse STRB1 but with the same pulse width. The fail signal or fail signal output from the same level comparator 2 is compared.
    Each of these timing comparators CMP1 and CMP2 outputs a logic "0" when the comparison result is a pass and a logic "1" when the comparison result is a fail.
    When the edge comparison mode is selected, a logic " 1 " (L level) output is supplied to the set terminal S of the multiplexer MUX1 and the clear terminal CL of the first flip-flop FF1. As a result, the multiplexer MUX1 is set to connect its input A to its output Q, and the first flip-flop FF1 is not cleared, and thus is in an operating state. Therefore, the comparison result of the first timing comparator CMP1 is stored in the first flip flop FF1, and the comparison result of the second timing comparator CMP2 is stored in the second flip flop FF2.
    In contrast, when the window comparison mode is selected, the logic " 1 " (H level) output is supplied to the set terminal S of the multiplexer MUX1 and the clear terminal CL of the first flip-flop FF1. In this case, the multiplexer MUX1 is set to connect the input B to the output Q. On the other hand, the first flip-flop FF1 is in the cleared state, and its Q output becomes logic "0" even if the comparison result of the first timing comparator CMP1 is supplied to the data terminal D. FIG. Therefore, in the window comparison mode, only the output of the timing comparison circuit 5 that is operating is in a state where it can be stored in the second flip-flop FF2 between the multiplexers MUX1.
    In this embodiment, the timing comparison circuit 5 comprises a series of test cycles constituting one test cycle with the first and second fail detection circuits 5a and 5b of the same circuit configuration each including a window strobe pulse generation circuit. In each period of the period, the generated first strobe pulses STRB1 are interleaved (alternatively divided) to form two strobe pulse strings of odd and even periods, and the first strobe pulse string of odd periods is set to the first. The first interleave circuit 8, which supplies the first strobe pulse of even periods to the second fail detection circuit 5b, to the fail detection circuit 5a of The second strobe pulse STRB2 is interleaved to form two strobe pulse strings of odd and even periods, and the second strobe pulse string of odd periods is assigned to the first fail detection circuit 5a with a second even number of cycles. Strobe pearl A second interleave circuit 9 having the same circuit configuration as the first interleave circuit 8 for supplying heat to the second fail detection circuit 5b and the first and second fail detection circuits 5a and 5b. And an output conversion circuit comprising seventh and eighth AND gates AND7 and AND8, an OR gate OR1, and a seventh flip-flop FF7 that alternately control the output of the < RTI ID = 0.0 >
    The first and second fail detection circuits 5a and 5b including the window strobe pulse generation circuit have the same circuit configuration as the timing comparison circuit 5 of the prior art shown in FIG. 4, respectively, and the operation thereof is also the same. Since the description thereof is omitted, the output of the first fail detection circuit 5a, and in this example, the inverted output XQ of the third flip-flop FF3 is connected to one input of the seventh AND gate AND7. The output of the second fail detection circuit 5b, in this example, the inverted output XQ of the fourth flip-flop FF4, is connected to one input of the eighth AND gate AND8. The outputs of these AND gates AND7 and AND8 are connected to the input of the multiplexer MUX1 between the OR gates OR1.
    The first interleave circuit 8 has a third AND gate AND3 and a fifth flip-flop having one input connected to the fifth flip-flop FF5 and the Q output of the flip-flop FF5. The fourth AND gate AND4 and the first strobe pulse STRB1 having one input connected to the XQ output of FF5) are inverted, and the clock terminals of the fifth flip-flop FF5 and the third and fourth The first inverter INV1 supplies to the other inputs of the AND gates AND and AND4, respectively, and the output of the third AND gate AND3 is the window strobe of the first pay detection circuit 5a. The output of the fourth AND gate AND4 is connected to the set terminal S of the set reset flip-flop S / R * FF1 that operates as a pulse generation circuit, and the output of the second fail detection circuit 5b It is connected to the set terminal S of the set reset flip-flop S / R * FF2 which operates as a window strobe pulse generation circuit.
    The second interleave circuit 9 has a fifth AND gate AND5 and a sixth flip-flop having one input connected to the sixth flip-flop FF6 and the Q output of the flip-flop FF6. The sixth AND gate AND6 and the second strobe pulse STRB2 having one input connected to the XQ output of the FF6 are inverted, and the clock terminals of the sixth flip-flop FF6 and the fifth and sixth The second inverter INV2 is supplied to the other inputs of the AND gates AND5 and AND6, respectively, and the output of the fifth AND gate AND5 is the set of the first fail detection circuit 5a. It is connected to the reset terminal R of the reset flip-flop S / R-FF1, and the output of the sixth AND gate AND6 is the set reset flip-flop of the second fail detection circuit 5b. It is connected to the reset terminal R of (S / R * FF2).
    In the third to sixth AND gates AND3 to 6, the input terminals are the inverting terminals, respectively, so that logic "1" is output only when logic "0" is input to the input terminal. Output logic "1".
    As described above, since the first and second interleave circuits 8 and 9 have the same circuit configuration, the operation of the first interleave circuit 8 will be described in detail below.
    First, in the initial state, since the fifth flip-flop FF5 is in the state cleared by the initial clear signal shown in FIG. 3AF, the Q output is logic "0" and the XQ output is logic "1". Since the output of the first inverter INV1 is logic "1", the outputs of the third and fourth AND gates AND3 and AND4 are logic "0", respectively. Therefore, both the reset and flip-flops S / R.FF1 and S / R.FF2 of the first and second fail detection circuits 5a and 5b are in the reset state.
    In this state, the test cycle is started, and in the first odd period, the first strobe pulse STRB1 shown in FIG. 28 is the first interleaver INV1 of the first interleave circuit 8. When supplied to the input of, the inverter "IN" outputs a logic "0", which is an inverted waveform of the first strobe pulse STRB1, as shown in FIG. 2I. Therefore, since the logic "0" is supplied to the clock terminal of the fifth flip-flop FF5, its Q output becomes logic "0", and its XQ output becomes logic "1". However, the third AND gate AND3 in the enabled state due to the logic "0" of the Q output of the fifth flip-flop FF5 has the logic "0" of the inverter INV1 at its other input. Since it is supplied, the gate is opened (turned ON) and a logic "1" is output. As a result, the set reset flip-flop S / R-FF1 of the first fail detection circuit 5a is set, and a logic "1" is output from the Q output thereof.
    When the first strobe pulse STRB1 of the first odd period ends, the input of the first inverter INV1 becomes logic "0", so the output becomes logic "1", and this logic "1" Is supplied to the clock terminals of the fifth flip-flop FF5 and to the third and fourth AND gates AND3 and AND4. As a result, the logic " 1 " of the data terminal D of the flip-flop FF5 is supplied to the Q output thereof, and the XQ output thereof becomes the logic " 1 ". Therefore, the third AND gate AND3 is turned off and the fourth AND gate AND4 is enabled this time.
    When the first strobe pulse STRB1 of the next period (the first even period) is supplied to the input of the first inverter circuit INV1, the output becomes a logic "0", so that the preceding period (the first The fourth AND gate AND4 enabled at the end of the first strobe pulse STRB1 of odd period) is turned on this time and outputs a logic "1". As a result, the set reset flip-flop S / R FF2 of the second fail detection circuit 5b is set, and a logic "1" is output from the Q output thereof.
    When the first strobe pulse STRB1 of the first even period ends, the input of the first inverter INV1 becomes logic "0", so the output becomes logic "1", and this logic "1". Is supplied to the clock terminals of the fifth flip-flop FF5 and the third and fourth AND gates AND3 and AND4. As a result, the logic "0" of the data terminal D of the flip-flop FF5 is supplied to the other Q output, and the XQ output thereof becomes the logic "1". Therefore, the fourth AND gate AND4 is turned off and the third AND gate AND3 is enabled again. The output waveform of the first inverter INV1 is shown in FIG. 21, the waveform of the Q output of the fifth flip-flop FF5 is shown in FIG. 2K, and the waveform of its XQ output is shown in FIG. 2L.
    Hereinafter, the first interleave circuit 8 repeats the above operation.
    As easily understood from the above operation description, the output of the third AND gate AND3 is as shown in Fig. 20, and the output of the fourth AND gate AND4 is shown in Fig. 2Q. Become together. Thus, the first strobe pulse STRB1 of each period is interleaved by the first interleave circuit 9 by the odd period strobe pulse STRB 1-1 and the even period strobe pulse STRB 1-2. It can be seen that.
    The second interleave circuit 9 also operates in the same manner as the first interleave circuit 8, and the second strobe pulse STRB2 of each period supplied to the input of the second interleaver INV2 is an odd period strobe. Since it is obvious to interleave the pulse STRB 2-1 with the even-numbered strobe pulse STRB 2-2, the output waveform of the second inverter INV2 is shown in FIG. 2J, and the sixth flip-flop ( The waveform of the Q output of FF6) is shown in FIG. 2M and the waveform of XQ thereof is shown in FIG. 2N, and the output waveform of the fifth AND gate AND5 is shown in FIG. 2P, and the output waveform of the sixth AND gate AND6 in FIG. Are shown in FIG. 2R and description of their operation is omitted.
    In this manner, the first and second strobe pulses STRB1 and STRB2 of each period are interleaved to the first and second interleave circuits 8 and 9, respectively, and the odd period strobe pulses of the two strobe pulses STRB1 and STRB2. (STRB 1-1- and STRB 2-1) are supplied to the first fail detection circuit 5a, and the even-numbered strobe pulses STRB 1-2 and STRB 2-2 are supplied to the second detection circuit 5B. ), The first and second fail detection circuits 5a and 5b operate as follows.
    In the first fail detection circuit 5a, since a logic "1" output is always applied to the data terminal D of the third flip-flop FF3, the odd period of the first strobe pulse STRB1 When the reset flip-flop S / R FF1 is set by supplying the strobe pulse STRB 1-1, and logic "1" is output from the Q output thereof, the third flip-flop FF3 The Q output becomes a logic "1".
    When the logic "1" is output from the Q output of the set reset flip-flop S / R FF1, the first AND gate AND1 is enabled, so that the logic "1" from the level comparator 2, that is, When a fail signal (Fig. 2A) is output and supplied to the first AND gate AND1, this fail signal is given to the clear terminal CL of the third flip-flop FF3 through the AND gate AND1. Therefore, the third flip-flop FF3 is cleared, and its XQ output becomes logic "1". In the XQ output of the third flip-flop FF3, the interleaved first strobe pulses STRB 1-2 are not supplied to the first fail detection circuit 5a in an even period, and thus, the first odd period of the next odd period. The state of logic " 1 " (fail) is maintained until the set reset flip-flop S / R / FF1 is set by the leading end of the strobe pulse STRB 1-1 of 1 (see also 3W).
    In this manner, the first AND gate AND1 has the first odd-numbered cycle after the set reset flip-flop S / R-FF1 is set by the first strobe pulse STRB 1-1 having an odd period. This signal is sent when the failure until the reset by the two strobe pulses STRB 2-1 is enabled and a fail signal (logical " 1 " output) comes from the level comparator 2. Therefore, the reset flip-flop S / R FF1 rises at the leading end of the first strobe pulse STRB 1-1 in odd periods, and the second strobe pulse STRB 2-1 in the same odd periods. It can be seen that the window strobe pulses W · STRB1 shown in FIG. The first AND gate AND1 is opened between the durations of the strobe pulses, and when a logic " 1 " output (fail signal) comes from the level comparator 2 (see also 3T). Therefore, when a fail occurs, one of the seventh AND gates AND7 is supplied to the input from the XQ output of the third flip-flop FF3 (a WP3W diagram). The logic " 1 " output from the XQ output section of this third flip-flop FF3 is the first strobe pulse STRB 1 which sets the set-set flip-flop S / R and FF1 at the next even period. Since -1) does not exist, it is retained until the set-set flip-flop S / R-FF1 is set by the leading end of the first strobe pulse STRB 1-1 of the next odd period. That is, the first odd period of the next odd period from the tip of the second strobe pulse STRB 2-1 of odd period during the period in which logic "1" is outputted at the XQ output of the third flip-flop FF3 is output. The area up to the front end of the strobe pulse STRB 1-1 (the area shown by oblique lines in FIG. 3) becomes fail confirmation data.
    Also in the second fail detection circuit 5b, since the logic " 1 " output is applied to the data terminal D of the fourth flip-flop FF4, the even period of the first strobe pulse STRB1 When the reset flip-flop S / R / FF2 is set by supplying the strobe pulses STRB 1-2 and the logic "1" is output from the Q output, the Q of the fourth flip-flop FF4 is output. The output becomes a logic "1".
    When the logic "1" is output from the Q output of the set reset flop S / R FF2, the second AND gate AND2 is enabled, so that the logic "1" from the level comparator 2, When the fail signal is output and supplied to the second AND gate AND2, the fail signal passes through the AND gate AND2 to the clear terminal CL of the fourth flip-flop FF4. Therefore, the fourth flip-flop FF4 is cleared and its XQ output is logic "1". The XQ output of the fourth flip-flop FF4 is not supplied to the second fail detection circuit 5b because the first interleaved strobe pulse STRB 1-1 is not supplied to the second fail detection circuit 5b in odd periods. The state of logic "1" (fail) is maintained until the set reset flip-flop S / R * FF2 is set by the leading end of the strobe pulse STRB 1-2 of 1 (see also 3Z). However, in this example, no fail occurs in the even period, so that the waveform of the XQ output of the fourth flip-flop FF4 remains logic " 0 " as shown in FIG. 3Z.
    As described above, the second AND gate AND2 has the second even-numbered cycle since the set reset flip-flop S / R-FF2 is set by the first strobe pulse STRB 1-2 of the even-numbered period. It is enabled until it is reset by the strobe pulse STRB 2-2, and when the fail signal (logical "1" output) comes from the level comparator 2, this signal is sent. Therefore, the set reset flip-flop S / R FF2 rises at the leading end of the first strobe pulse STRB 1-2 in even periods, and the second strobe pulse STRB 2-2 in the same even periods. It can be seen that the window strobe pulses W · STRB2 shown in FIG. Between the durations of the strobe pulses, a second AND gate AND2 is opened and passes through the logic " 1 " output (fail signal) from the level comparator 2 (see also the third V). However, in this example, no fail occurs in the even period, so the output of the second AND gate AND2 remains as logic " 0 ". Therefore, if a fail occurs, the set-up flip-flop (S / R, ...) from the XQ output of the fourth flip-flop FF4 to the leading end of the first strobe pulse STRB 1-2 of the next even period. The logic " 1 " output is supplied to one input of the eighth AND gate AND8 until FF2) is set.
    Here, in the XQ output of the fourth flip-flop FF4 shown in FIG. 3Z, the region shown by the oblique line becomes the fail confirmation data during the logic " 1 " outputted when the fail signal arrives. . This fail correction data is a period from the leading end of the second strobe pulse STRB 2-2 of even period to the leading end of the first strobe pulse STRB 1-2 of next even period.
    The seventh and eighth AND gates AND7 and AND8 are controlled on / off by the Q output XQ outputs of the seventh flip-flop FF7, respectively. In the seventh flip-flop FF7, its data terminal D is connected to its XQ output, and the second strobe pulse STRB2 is supplied from the timing generator 6 to the clock terminal. In the initial state, the seventh flip-flop FF7 is cleared by the initial clear signal shown in FIG. 3AF, so that its Q output is logic "0" and its XQ output is logic "1". Therefore, in the initial state, the seventh AND gate AND7 is turned off and the eighth AND gate AND8 is enabled.
    These AND gates AND7 and AND8 remain in their initial state until a test cycle is initiated and a second strobe pulse STRB2 is generated. When the second strobe pulse STRB2 is generated, the logic " 1 " of the data terminal D of the seventh flip-flop FF7 is supplied to its Q output, so the Q output becomes logic " 1 " The XQ output is a logic "0". Therefore, the seventh AND gate AND7 is enabled, and the eighth AND gate AND8 is turned off. This state continues until the second strobe pulse STRB2 is generated in the next period.
    Since the logic "0" of the data terminal D of the seventh flip-flop FF7 is supplied to the Q output by the generation of the next second strobe pulse STRB2, the Q output becomes a logic "0". The XQ output thereof becomes a logic "1". Therefore, the seventh AND gate AND7 is turned off, and the eighth AND gate AND8 is enabled. This state continues until the second strobe pulse STRB2 is generated in the next period.
    As can be easily understood in the above description, the seventh AND gate AND7 is turned on in the middle of the first odd period (in this example, after a time period corresponding to half cycle), and the first even period. In the middle of (in this example, after a time period corresponding to ½ cycle), it is turned off. In contrast, the eighth AND gate AND8 is turned on in the middle of the first even period (in this example, after a time elapsed corresponding to the half cycle), and in the middle of the second odd period (½ cycle in this example). After the time elapsed corresponding to the control unit is turned off. The same operation is repeated as shown in FIGS. 3X and 4A below. Thus, the seventh and eighth AND gates AND7 and AND8 'are alternately turned on, and the XQ output of the third flip-flop FF3 and the XQ output of the fourth flip-flop FF4 are alternately ORed. It is supplied to the B input of the multiplexer MUX1 through the gate OR1. As a result, timing comparison was performed on the B input of the multiplexer MUX1 in the window comparison mode in the order of first odd period → first even period → second odd period → second even period → ..... Since the result is supplied, it is equal to the period of the data output from the level comparator 2. In other words, it returns to the cycle of the original test cycle.
    When window comparison is performed by the timing comparison circuit of the above configuration, each fail confirmation data is not cleared by the leading end of the window strobe pulse of the next period (because it is cleared by the leading end of the window strobe pulse of the next cycle). The width of the area of the definite data (the area shown by the oblique line in FIG. 3) can be significantly expanded. For this reason, in order to expand the range of window comparison, as shown by the arrow in FIG. 2, the time of occurrence of the second strobe pulse STRB2 is delayed to approach the first strobe pulse STRB1 of the next period. Even if the signal is generated at the same time point as the first strobe pulse STRB1 of the next period as shown in FIG. 2, that is, even if the timing comparison is performed continuously with the minimum off time Min as an area. As described above, since the area of the fail confirmation data extends to a part of the next cycle, the area of the fail confirmation data is reduced, and setup / required for storing fail data from the second flip-flop FF4. It will not be shorter than the hold time. In this way, the fail data can be stored completely.
    Therefore, according to this invention, since the minimum off time (taumin) can be eliminated, even if a fail occurs in any time, it can be detected. Therefore, as in the prior art, it is not necessary to perform the test of the DUT by separating the circuits two times with the timing off, so that the test period can be shortened and the test apparatus can be used very efficiently.
    In the above embodiment, the case where the present invention is applied to the semiconductor memory test apparatus has been described. However, the present invention can be applied to an apparatus for testing a device other than a semiconductor such as a semiconductor device or an electronic component other than the memory. It is natural to be obtained. In the above embodiment, the window strobe pulse generation circuit is combined with the first and second fail detection circuits 5a and 5b, respectively, but the window strobe pulse generation circuit and the fail detection circuit may be separate circuits. Further, although the first and second fail detection circuits 5a and 5b have the same circuit configuration, and the first and second interleave circuits 8 and 9 have the same circuit configuration, the first and second fail detection circuits 5a and 5b have the same circuit configuration. The fail detection circuits 5a and 5b need not necessarily have the same circuit configuration, and likewise, the first and second interleaved circuits 8 and 9 need not necessarily have the same circuit configuration. However, if the circuit configuration is the same as in the above embodiment, it is easy to manufacture, so that the productivity is good, the cost is reduced, the characteristics are provided, and the accuracy is improved.
    As apparent from the above description, in the present invention, a fail signal is applied to the output signal from the level comparator during the duration of the supplied window strobe pulse and the first and second window strobe pulse generation circuits alternately generating the window strobe pulses. A first strobe pulse train having odd periods of first strobe pulses provided by the first and second fail detection circuits and the first and second interleaved circuits respectively for detecting whether there exists; Interleaving two pulse strings of the first strobe pulse string of and even periods, operating the first window strobe pulse generating circuit by the first strobe pulse string of odd periods, and simultaneously performing the second window strobe pulse generating circuit. The second strobe by the first strobe pulse train and the second interleave circuit. Interleaving the pulses into two pulse strings of an odd period of the second strobe pulse train and an even period second strobe pulse train, and operating the first window strobe pulse generation circuit by the second strobe pulse train of the odd period. The operation of the second window strobe pulse generation circuit is stopped by the second strobe pulse train of even periods, respectively, whereby the window strobe pulses for odd periods and the window strobe pulses for even periods are separated from the first and second window strobe pulse generation circuits. Is generated to detect whether or not a failure has occurred in the data (signal) output from the level comparator during the duration of these odd period window strobe pulses and even period window strobe pulses. As a result, even if the time of occurrence of the second strobe pulse is close to the time of occurrence of the first strobe pulse of the next period or the same time of occurrence of the first strobe pulse of the next period, the first and second Since the output of the fail detection circuit can be cleared at the leading end of the window strobe pulse of the next period immediately, the width of the fail determination data area can be expanded. Therefore, a fail confirmation data area longer than the minimum set up / hold time (minimum off time) required for storing the outputs of the first and second fail detection circuits in the storage means can be secured. The minimum off time at which the timing comparison between the two can not be performed can be made zero. Therefore, even if a fail occurred at any point in time by one test, the test period can be detected very short, and there is an advantage that the test apparatus can be used very efficiently.
    权利要求:
    Claims (7)
    [1" claim-type="Currently amended] A level comparator for comparing the level of the output signal read out from the device under test to a high level or low level reference;
    A timing generator for outputting strobe pulses that are clock pulses for timing comparison;
    A second strobe pulse that is actuated by a first strobe pulse that rises at the start of each period supplied from the timing generator, and at the same time the first strobe pulse rises in each period and rises after a predetermined time elapses; The result of comparison is supplied from the level comparator in a window strobe pulse generation circuit which is inactivated by the operation and generates a window strobe pulse at each period and the duration of the window strobe pulse output from the window strobe pulse generation circuit. A timing comparison circuit comprising a fail detection circuit for detecting whether a fail signal is present in the signal of < RTI ID = 0.0 >
    A device testing apparatus comprising a storage means for storing a fail signal output from the timing comparison circuit,
    The timing comparison circuit
    A first window strobe pulse generation circuit for generating a window strobe pulse,
    The signal of the comparison result is supplied from the level comparator, and during the duration of the window strobe pulse supplied from the first window strobe pulse generation circuit, it is detected whether a fail signal is present in the signal of the crossover result, and a fail signal A first fail detection circuit that maintains the detection result from the first window strobe pulse generation circuit to the time when the tip of the next window strobe pulse is generated when is detected;
    A second window strobe pulse generation circuit for generating window strobe pulses,
    The signal of the comparison result is supplied from the level comparator, and during the duration of the window strobe pulse supplied from the second window strobe pulse generation circuit, it is detected whether a fail signal is present in the signal of the comparison result, and a fail signal A second fail detection circuit which maintains the detection result from the second window strobe pulse generation circuit until a point where the tip of the next window strobe pulse is generated when is detected;
    In each cycle of a series of cycles constituting one test cycle, the first strobe pulses generated from the timing generator are interleaved to form two strobe pulse trains of odd and even periods, and the first strobe of odd periods. Supplying a pulse train to the first window strobe pulse generation circuit to operate the pulse generation circuit, and supplying an even period of the first strobe pulse to the second window strobe pulse generation circuit to operate the pulse generation circuit. A first interleave circuit,
    In each cycle of a series of test cycles, the second strobe pulses generated from the timing generator are interleaved to form two strobe pulse trains of odd and even periods, and the second strobe pulse trains of odd periods are designated as the first window. A second supply of the strobe pulse generation circuit to stop the operation of the pulse generation circuit, and a second even strobe pulse of the even period to the second window strobe pulse generation circuit to stop the operation of the pulse generation circuit. Interleaved circuit,
    And
    The first and second window strobe pulse generation circuits are alternately operated by the first and second interleave circuits, so that time is lost between the window strobe pulses alternately generated by these window strobe pulse generation circuits. Timing comparison circuit, characterized in that no.
    [2" claim-type="Currently amended] 2. The timing comparison circuit according to claim 1, further comprising an output conversion circuit for alternately converting the outputs of the first and second fail detection circuits and supplying them to the storage means.
    [3" claim-type="Currently amended] 3. The output conversion circuit of claim 2, wherein the output conversion circuit alternately converts two AND gates, one OR gate taking a logic value of the outputs of these AND gates, and an output of the two AND gates to the OR gate. A single flip-flop, one AND gate having one input connected to an output of the first fail detection circuit and the other input connected to a non-inverting output of the flip flop. The other AND gate has its one input connected to the output of the second fail detection circuit, its other input connected to the inverted output of the flip-flop, and the output of the OR gate to the storage means. Timing comparison circuit, characterized in that supplied.
    [4" claim-type="Currently amended] 2. The circuit of claim 1, wherein the first and second fail detection circuits have the same circuit configuration, each of which consists of one AND gate and one flip-flop, and on one input of the AND gate from the level comparator. The signal of the comparison result is supplied, and the other input is supplied with the window strobe pulse from the corresponding window strobe pulse generation circuit, the output of the AND gate is supplied to the clear terminal of the flip flop, and the clock of the flip flop The terminal is supplied with a window strobe pulse from a corresponding window strobe pulse generation circuit, and a fail signal detected from the inverted output of the flip-flop is output.
    [5" claim-type="Currently amended] The method of claim 1, wherein the first and second window strobe pulse generation circuit,
    Each set consists of a set flip flop,
    The set flip-flop of the first window strobe pulse generation circuit is set by a first strobe pulse of odd periods supplied to the first interleave circuit, and is an odd number supplied from the second interleave circuit at the same time. Reset by a second strobe pulse of a period to generate the window strobe pulse,
    The set reset flip-flop of the second window strobe pulse generation circuit is set by the first strobe pulse of an even period supplied from the first interleave circuit, and is an even number supplied from the second interleave circuit at the same time. And reset by the second strobe pulse of the period to generate the window strobe pulse.
    [6" claim-type="Currently amended] 2. The apparatus of claim 1, wherein the first and second interleave circuits have the same circuit configuration, one flip-flop each having one inverter and an output signal from the inverter supplied to a clock terminal, The output signal is inverted and is composed of two AND gates of first and second supplied to each input, the non-inverting output of the flip-flop is inverted to the other input of the first AND gate. And an inverted output of the flip-flop is supplied to its data terminal and inverted and supplied to the other input of the second AND gate.
    [7" claim-type="Currently amended] 10. The flip-flop of claim 6, wherein a first strobe pulse is supplied to an input of the inverter of the first interleaved circuit, and an output of the first AND gate is set by the first window strobe pulse generation circuit. A set terminal of the second AND gate is supplied to a set terminal of the reset flip-flop of the second window strobe pulse generation circuit,
    A second strobe pulse is supplied to an input of the inverter of the second interleave circuit, and an output of the first AND gate is supplied to a reset terminal of the reset flip-flop of the first window strobe pulse generation circuit. Become,
    And the output of the second AND gate is supplied to the reset terminal of the reset flip-flop of the second window strobe pulse generation circuit.
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    同族专利:
    公开号 | 公开日
    DE19651713A1|1997-07-03|
    JPH09222463A|1997-08-26|
    DE19651713C2|1999-08-19|
    US5732047A|1998-03-24|
    KR100206509B1|1999-07-01|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1995-12-12|Priority to JP32332195
    1996-12-12|Application filed by 오오우라 히로시, 가부시키가이샤 아드반테스트
    1996-12-12|Priority to JP95-323321
    1996-12-12|Priority to JP8331892A
    1998-09-15|Publication of KR19980046278A
    1999-07-01|Application granted
    1999-07-01|Publication of KR100206509B1
    优先权:
    申请号 | 申请日 | 专利标题
    JP32332195|1995-12-12|
    JP95-323321|1996-12-12|
    JP8331892A|JPH09222463A|1995-12-12|1996-12-12|Timing comparison circuit for device inspecting equipment|
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